1. Field of the Invention
The present invention generally relates to integrated circuit devices that generate voltages internally and, more particularly, to memory devices that rely on a variety of internally generated voltages that may be varied with temperature to improve their performance.
2. Description of the Related Art
In recent years, the demands for low-power and low-voltage memory have increased tremendously as portable and handheld devices, such as personal digital assistants (PDAs), cellular phones, and notebook computers have become increasingly popular. Simply put, the less power these devices consume, the longer they may operate off of their batteries and/or the size and weight of their batteries may be reduced, enhancing portability in either case.
One of the more popular types of memory used in these devices, due to the available density, speed, and relatively low cost, is dynamic random access memory (DRAM). DRAM devices are referred to as dynamic (as opposed to static) because their memory cells must be refreshed periodically (within a given retention time) in order to maintain data stored therein. Typically, a DRAM device can be placed in a self-refresh mode, whereby the DRAM devices generates signals internally (i.e., self-refresh signals) to refresh each row of memory cells. DRAM devices are typically put into a self-refresh mode when a system is placed in a standby or low power mode, which may be entered quite aggressively in order to conserver power in portable devices.
As a result, one of the main contributing factors to power consumption in DRAM devices is self-refresh current generated during standby modes. Accordingly, reducing self-refresh current is one of the most important challenges in low-power and low-voltage DRAM design (or any other types of memory that require refresh, such as PSRAM). The self-refresh current consists of current consumed by switching transistors in memory cell arrays and peripheral circuitry, as well as DC current. The DC current is typically caused by the flow of current through a transistor while in the off state (i.e., the switching voltage of the transistor VGS is below the threshold voltage VTH), generally referred to as subthreshold leakage current. In the past, the DC current contribution was generally small and array current was the larger factor in the self-refresh current. However, as memory density increases, the number of transistors increases accordingly, such that DC current due to subthreshold leakage current increases drastically. Thus, to produce a low power memory device, reducing subthreshold leakage current is highly desirable.
Subthreshold leakage current depends on channel width and length, threshold voltage, gate-source voltage, and drain-source voltage of the transistors. Since the subthreshold voltage is a function of drain-source voltage, transistors using a boosted wordline voltage, commonly referred to as VPP, consume more subthreshold leakage current. VPP is mainly used in row decoder circuits and is applied to the cell gate (via a word line) to store high logic data. In order to compensate for the voltage drop of VTH across the cell switching transistor and ensure a full bit line high logic voltage level VBLH is transferred to the cell, VPP is typically set to a level one cell threshold voltage VTH above VBLH.
As VPP is outside the typical supply voltage range, memory devices typically include a voltage generator, including a charge pump, to generate VPP. FIG. 1 illustrates an exemplary conventional VPP generator 100. In addition to a charge pump 102, the VPP generator 100 also includes a VPP detector 104, a VPP reference 106, a comparator 108, and a VPP oscillator 110. Generally speaking, the reference 106 sets the desired VPP level while detector 104 is configured to detect a minimum VPP level. As illustrated, both the detector 104 and reference 106 may be configured as simple voltage dividers using resistors R1–R4, chosen such that the output of the detector 104 matches the output of the reference 106 at the minimum VPP level. Accordingly, outputs from the reference and detector may be input to the comparator 108 such that, when the detected VPP level drops below the minimum VPP level set by the reference, the output of comparator 108 enables the VPP oscillator 110 which drives the pump 102 to restore the original target voltage level.
Utilizing this conventional VPP generator 100, VPP stays at substantially the same voltage level over a wide operating temperature range. As previously described, the target VPP level is typically chosen to be higher than the high bit line logic level (VBLH) by the cell threshold voltage VTH, which is highest at low temperatures. Accordingly, the target VPP level is typically set high enough to accommodate this worst case (maximum) cell threshold voltage. Unfortunately, this results in an unnecessarily high VPP level and increased subthreshold leakage current when the cell transistor threshold voltage is lower at higher temperatures.
Accordingly, there is a need for techniques and apparatus for improving device performance (e.g., reducing subthreshold leakage current or improving refresh times) in a memory device, preferably by varying one or more internally generated voltage levels based on the device temperature.